Dhruv Patel did an excellent job demonstrating his 16nm CMOS optical receiver and reporting the results at ECOC in Basel, Switzerland, in September 2022.
Prof. Chan Carusone at CICC 2022
Prof. Chan Carusone presented at an Educational Session on Architectural Considerations of 100+Gbps Wireline Transceivers and participated in an industry panel addressing the questions “Is Photonics Going to Save Wireline” at CICC in Irvine, California this week.
ISL Reports 112Gbps CMOS Optical Receiver
Ph.D. candidate Dhruv Patel reported the results of his 112Gbps TIA in 16nm FinFET CMOS at CICC 2022. Check out the demo video on the right…
Prof. Chan Carusone elevated to IEEE Fellow
“The most inspiring and innovative people I’ve encountered are IEEE Fellows, and I’m proud to count myself among them. But I’m most proud of seeing my grad students accomplish amazing things during and after their degree.”
Best Paper Award at DesignCon2021
Congrats to Ph.D. candidate Ming Yang for landing a Best Paper Award at DesignCon2021! Thanks to our great collaborators and co-authors Shayan Shahramian, Henry Wong and Petar Krotnev. There are dozens, or even hundreds, of parameters in modern wireline transceivers. Getting them all just right is a major challenge that demands advanced optimization algorithms during architectural design, in the lab, and in the field.
M. Yang, S. Shahramian, H. Wong, P. Krotnev, A. Chan Carusone, “Global Optimization of Wireline Transceivers for Minimum Post-FEC vs. Pre-FEC BER,” DesignCon, San Jose, California, August 2021. [PDF] [PDF Slides]
Design Methodologies for Low-Jitter CMOS Clock Distribution
Distributing a low-jitter GHz clock across a CMOS chip isn’t easy. Learn how in our open-access invited paper in the Open Journal of the IEEE Solid-State Circuits Society. Our design methodologies are backed up by measurements of a 16nm FinFET prototype.
Lighting Up the World of Computing, Communication, and Connectivity
I’m sitting on a panel discussion, “Lighting Up the World of Computing, Communication, and Connectivity,” at UofT’s Engineering Research Days, June 25-26.
Optimizing Transceivers to Minimize BER
Although our communication links are generally designed and optimized to maximize SNR, that doesn’t necessarily minimize the bit error rate. The situation gets worse once forward error correction (FEC) is taken into account. Join us at ISCAS 2021 in the special session on Advanced Energy-Efficient Wireline & Optical Communications where Ph.D. candidate Ming Yang will present our paper on the relevant tradeoffs in modern wireline links. He’ll show how we can do better!
Post-Doctoral Fellow Position
We’ve got an exciting opportunity to collaborate on a new research project in our group. See the details here.
Prof. Chan Carusone Named Editor-In-Chief of SSC-L
I’m very excited to be the new Editor-in-Chief of the IEEE Solid-State Circuits Letters (SSC-L)!
SSC-L publishes short papers on novel integrated circuit (IC) ideas and experimental results with a faster turnaround than its sister publication, the Journal of Solid-State Circuits. Prof. Behzad Razavi was the publication’s founding Editor-in-Chief. Over the past three years, he assembled a distinguished editorial board and editorial review board and oversaw the publication’s steady growth. We should all be grateful for his service to the community.
I now look forward to working with SSC-L’s outstanding volunteers to build on the publication’s unique strengths as a venue for IC research. Our ability to publish a peer-reviewed paper to a worldwide audience within three months of submission is tremendously valuable to many authors. Likewise, readers trying to stay abreast of our fast-moving field benefit from a constant stream of the latest results. I hope to raise awareness of these strengths while maintaining our high-quality peer-review process on a fast turnaround. Doing so will accelerate progress on significant IC research problems and facilitate the rapid translation of research results into tangible benefits for all of humanity.