ISSCC 2021 Forum on Wireline Transceivers

I’m chairing a forum on Optical and Electrical Transceivers for 400GbE and Beyond at this year’s International Solid-State Circuits Conference. Eight 45-minute forum presentations from experts in industry and academia go live on February 12. We’ll then have a live Q&A with the presenters on February 22. Register for the conference to get access at

I’m looking for an accomplished researcher to help lead our efforts on high-speed optoelectronic computing and communication. As a post-doctoral fellow, you’d have the unique opportunity to collaborate across disciplines and sectors (academia & industry) on a well-resourced project in an emerging field. If you’re interested in joining us and have a background in IC design and/or integrated photonics, please send your CV to within the next 10 days.

Simulations to accurately predict error probabilities below 10-15 in communication links with forward error correction used to take 1000’s years on a typical desktop. Ph.D. Candidate Ming Yang has developed techniques that allow us to do it in under a minute. With the help of our industry partners, the techniques have been validated on real wireline links at 60 Gbps. If you missed him present the techniques at DesignCon in Santa Clara, January 2020, then read about it in our recently-published open-access paper.

Two ISL alumni presented back-to-back to a packed crowd of over 400 researchers at the ISSCC 2019 session on “Advanced Wireline Techniques” Wednesday afternoon, February 20th in San Francisco: congratulations to Shayan Shahramian and Masum Hossain. In total, six ISL alumni were authors on ISSCC papers this year.

Prof. Chan Carusone delivered seminars in Melbourne and Sydney, Australia on CMOS Optical Transceiver circuits, March 15 and 28th, 2018.

Congratulations to ISL Ph.D. candidate Luke Wang who will be presenting his work on a “A 64Gb/s PAM-4 Transceiver Utilizing an Adaptive Threshold ADC in 16nm FinFET” at the 2018 International Solid-State Circuits Conference in San Franscisco.  The work is part of our collaboration with Huawei Canada, and is the only university-led paper at the conference describing a circuit in 16nm CMOS.  Check out the conference advance program here.