Research News – Integrated Systems Laboratory

Best Paper at DesignCon 2023

May 10, 2023 by tcc

For the second time in three years, ISL research has been recognized with a Best Paper Award at DesignCon, the premier high-speed communications and system design conference and expo for chip, board, and systems design engineers. Titled “Statistical BER Analysis of Concatenated FEC in Multi-Part Links,” the paper tackles a pressing challenge in 200+Gbps wireline links: how to evaluate and ensure post-FEC BER performance prior to finalizing a link architecture.

Congratulations to Richard Barrie and Ming Yang for this well deserved accolade!

160Gbps Optical Receiver Results at ECOC

October 5, 2022 by tcc

Dhruv Patel did an excellent job demonstrating his 16nm CMOS optical receiver and reporting the results at ECOC in Basel, Switzerland, in September 2022.

CICC 2022 Outstanding Student Paper Award

May 10, 2023August 10, 2022 by tcc

Our work showing the potential for CMOS optical transceivers at 100+Gbps continues to get attention. Congratulations Dhruv Patel and Alireza Sharif Bakhtiar for bringing home the Outstanding Student Paper Award at CICC 2022!

Prof. Chan Carusone at CICC 2022

April 24, 2022 by tcc

Prof. Chan Carusone presented at an Educational Session on Architectural Considerations of 100+Gbps Wireline Transceivers and participated in an industry panel addressing the questions “Is Photonics Going to Save Wireline” at CICC in Irvine, California this week.

ISL Reports 112Gbps CMOS Optical Receiver

April 24, 2022 by tcc

Ph.D. candidate Dhruv Patel reported the results of his 112Gbps TIA in 16nm FinFET CMOS at CICC 2022. Check out the demo video on the right…

Prof. Chan Carusone elevated to IEEE Fellow

January 9, 2022January 6, 2022 by tcc

“The most inspiring and innovative people I’ve encountered are IEEE Fellows, and I’m proud to count myself among them. But I’m most proud of seeing my grad students accomplish amazing things during and after their degree.”

ECE Professors Tony Chan Carusone and Joyce Poon named IEEE Fellows

Best Paper Award at DesignCon2021

January 3, 2022 by tcc

Congrats to Ph.D. candidate Ming Yang for landing a Best Paper Award at DesignCon2021! Thanks to our great collaborators and co-authors Shayan Shahramian, Henry Wong and Petar Krotnev. There are dozens, or even hundreds, of parameters in modern wireline transceivers. Getting them all just right is a major challenge that demands advanced optimization algorithms during architectural design, in the lab, and in the field.

M. Yang, S. Shahramian, H. Wong, P. Krotnev, A. Chan Carusone, “Global Optimization of Wireline Transceivers for Minimum Post-FEC vs. Pre-FEC BER,” DesignCon, San Jose, California, August 2021. [PDF] [PDF Slides]

Design Methodologies for Low-Jitter CMOS Clock Distribution

October 14, 2021 by tcc

Distributing a low-jitter GHz clock across a CMOS chip isn’t easy. Learn how in our open-access invited paper in the Open Journal of the IEEE Solid-State Circuits Society. Our design methodologies are backed up by measurements of a 16nm FinFET prototype.

Lighting Up the World of Computing, Communication, and Connectivity

June 24, 2021 by tcc

I’m sitting on a panel discussion, “Lighting Up the World of Computing, Communication, and Connectivity,” at UofT’s Engineering Research Days, June 25-26.

Optimizing Transceivers to Minimize BER

May 5, 2021 by tcc

Although our communication links are generally designed and optimized to maximize SNR, that doesn’t necessarily minimize the bit error rate. The situation gets worse once forward error correction (FEC) is taken into account. Join us at ISCAS 2021 in the special session on Advanced Energy-Efficient Wireline & Optical Communications where Ph.D. candidate Ming Yang will present our paper on the relevant tradeoffs in modern wireline links. He’ll show how we can do better!