Graduate student Adesh Garg presented the world’s fastest decision feedback equalizer, operating at 40 Gb/s, at the Compound Semiconductor IC Symposium in Palm Springs, California.

A new programmable filter topology developed by graduate student Jonathan Sewter was presented at the Custom Integrated Circuits Conference in San Jose, California.  At 40 Gb/s, this broke our own speed record for high-speed equalization in CMOS.

The world’s fastest CMOS equalizer circuit was presented at the 2005 VLSI Circuit Symposium in Kyoto, Japan.  Developed by graduate student Jonathan Sewter in a 90-nm CMOS technology, this 3-tap filter is capable of equalizing 30-Gb/s NRZ data.

Prof. Chan Carusone presented a full-day short course on “Integrated Circuit Multi-Gb/s Chip-to-chip Transceivers” to the Singapore Chapter of the IEEE Circuits and Systems Society.

Prof. Chan Carusone presented a tutorial on “Analog Adaptive Filters” at the 2003 IEEE International Symposium on Circuits and Systems in Bangkok, Thailand.

Prof. Chan Carusone received the Canada Research Chair in Integrated Systems.