Prof. Chan Carusone gave an invited presentation at ASICON 2007 in Guilin, China on “High-Speed Baud-Rate Clock and Data Recovery”.
Congratulations to Kentaro Yamamoto, winner of the Best Student Paper Award at the 2007 Custom Integrated Circuits Conference for his paper entitled “A Delta-Sigma Modulator with a Widely Programmable Center Frequency and 82-dB Peak SNDR“. In that paper, we report on a delta-sigma modulator for reconfigurable radio terminals. Its passband is arbitrarily programmable, yet its performance comparable to the world’s very best fixed-passband modulators.
I presented at the CMOS Emerging Technologies Workshop in Whistler, BC. Some of that material will appear in a chapter of the book Circuits for Nanotechnology: Communications, Imaging, and Sensing to be published in late 2008.
Prof. Chan Carusone gave an invited presentation to the IEEE LEOS Summer Topical on “Advanced Digital Signal Processing in Next Generation Fiber Optic Transmission” in Portland, Oregon.
Congratulations to Shahriar Shahramian, a Ph.D. student in our group, who received the Best Paper Award from the 2005 Compound Semiconductor Integrated Circuits Symposium for his paper entitled, “A 40-GSamples/Sec Track & Hold Amplifier in 0.18μm SiGe BiCMOS Technology”! In that paper, he describes the analog front-end for an A/D converter operating more than two times faster than any other track-and-hold with comparable performance.
Prof. Chan Carusone presented research talks to the Vancouver Chapter of the IEEE Solid-State Circuits Society, the University of Calgary and the University of Alberta.
PhD candidate Ahmad Darabiha presented the world’s fastest FPGA implementation of an iterative FEC decoder at the 2006 International Symposium on Circuits and Systems in Kos, Greece. His LDPC decoder obtained a throughput of 650 Mb/s on U of T’s TM-4 rapid prototyping platform.
Graduate student Adesh Garg presented the world’s fastest decision feedback equalizer, operating at 40 Gb/s, at the Compound Semiconductor IC Symposium in Palm Springs, California.
A new programmable filter topology developed by graduate student Jonathan Sewter was presented at the Custom Integrated Circuits Conference in San Jose, California. At 40 Gb/s, this broke our own speed record for high-speed equalization in CMOS.