It was a pleasure to deliver the keynote at the premier international conference focused on advanced and emerging challenges in electrical modeling, analysis, and design of electronic interconnections, packages, and systems. EPEPS was held right here at the University of Toronto in October 2024.
Prof. Chan Carusone’s keynote presentation on Chiplets and AI from this year’s HOT Interconnects conference is now live on YouTube.
For the second time in three years, ISL research has been recognized with a Best Paper Award at DesignCon, the premier high-speed communications and system design conference and expo for chip, board, and systems design engineers. Titled “Statistical BER Analysis of Concatenated FEC in Multi-Part Links,” the paper tackles a pressing challenge in 200+Gbps wireline links: how to evaluate and ensure post-FEC BER performance prior to finalizing a link architecture.
Congratulations to Richard Barrie and Ming Yang for this well deserved accolade!
Dhruv Patel did an excellent job demonstrating his 16nm CMOS optical receiver and reporting the results at ECOC in Basel, Switzerland, in September 2022.
Our work showing the potential for CMOS optical transceivers at 100+Gbps continues to get attention. Congratulations Dhruv Patel and Alireza Sharif Bakhtiar for bringing home the Outstanding Student Paper Award at CICC 2022!
Prof. Chan Carusone presented at an Educational Session on Architectural Considerations of 100+Gbps Wireline Transceivers and participated in an industry panel addressing the questions “Is Photonics Going to Save Wireline” at CICC in Irvine, California this week.
Ph.D. candidate Dhruv Patel reported the results of his 112Gbps TIA in 16nm FinFET CMOS at CICC 2022. Check out the demo video on the right…
“The most inspiring and innovative people I’ve encountered are IEEE Fellows, and I’m proud to count myself among them. But I’m most proud of seeing my grad students accomplish amazing things during and after their degree.”
Congrats to Ph.D. candidate Ming Yang for landing a Best Paper Award at DesignCon2021! Thanks to our great collaborators and co-authors Shayan Shahramian, Henry Wong and Petar Krotnev. There are dozens, or even hundreds, of parameters in modern wireline transceivers. Getting them all just right is a major challenge that demands advanced optimization algorithms during architectural design, in the lab, and in the field.
M. Yang, S. Shahramian, H. Wong, P. Krotnev, A. Chan Carusone, “Global Optimization of Wireline Transceivers for Minimum Post-FEC vs. Pre-FEC BER,” DesignCon, San Jose, California, August 2021. [PDF] [PDF Slides]
Distributing a low-jitter GHz clock across a CMOS chip isn’t easy. Learn how in our open-access invited paper in the Open Journal of the IEEE Solid-State Circuits Society. Our design methodologies are backed up by measurements of a 16nm FinFET prototype.
