Prof. Chan Carusone presented a tutorial on Signal Integrity Analysis for Gb/s Links at the International Solid-State Circuits Conference in San Francisco February 5, 2017. Signal integrity analysis permits circuit designers to model and evaluate high-speed I/O with fast simulations, both for quick evaluation of design alternatives and accurate high-level verification. This tutorial covers theoretical underpinnings and practical tools for behavioral modeling and simulation of wireline chip-to-chip links. Attendees learn to accurately model lossy interconnect, packaging parasitics, and transceiver front-ends. Nondeterministic impairments such as noise and jitter, and the modeling of linear and decision-feedback equalization, are also treated. Analysis techniques amenable to both circuit-level (netlist) simulators and high-level modeling (e.g. Matlab) tools are covered.