Prof. Chan Carusone’s research overview on High-Speed Digital I/O appeared in the fall 2015 issue of the IEEE Solid-State Circuits Magazine.

Prof. Chan Carusone delivered an IEEE SSCS Distinguished Lecture at the University of Texas at Austin on the topic of CMOS Optical Transceivers.

ee-timesAfter presenting it at CICC 2015 in San Jose, our work on ultra-short-reach die-to-die links has been featured in an EETimes article.

Die2DieLinkWith support from partners CMC Microsystems and Huawei Canada, Behzad Dehlaghi has designed chips to launch signals at extremely high speeds, 20 Gb/s per lane, and a miniature silicon layer called an interposer to connect two chips together. The results will be presented at the Custom Integrated Circuits Conference in San Jose in September. Read the full story.

masumi_ofc2015ISL researcher Masumi Shibata presented her CMOS 26Gb/s VCSEL driver at the Optical Fiber Conference, OFC 2015 in Los Angeles alongside presenters and session chairs from Finisar, IBM, Hitachi, and Fujitsu.

Shayan

Congratulations to Ph.D. candidate Shayan Shahramian for winning the Best Young Scientist Paper Award at the 2014 European Solid-State Circuits Conference in Lido, Italy. Shayan’s paper was the first to combine multiple infinite & finite impulse response filters into the same decision feedback equalizer at 10Gb/s, while also establishing a new bar for energy efficiency in digital I/O.

Prof. Chan Carusone will present a half-day tutorial on the Modeling and Applications of Injection Locked Oscillators at the 2015 NEWCAS conference in Grenoble, France, June, 2015.

ESSCirC 2014

Congratulations to ISL researcher, Shayan Shahramian, on receiving an ADI Outstanding Student Designer award at ISSCC in San Francisco.

CMC Webinar Dec 2014

ISL researchers delivered a webinar to the CMC community summarizing our work on energy-efficient high density interconnects.

ESSCirC 2014

ISL graduate students present two papers at the European Solid-State Circuits Conference in Venice, Italy, including work on high-speed time-interleaved ADCs and a low-power DFE for high-speed I/O.