Publications

T. Chan Carusone, D. Johns, and K. Martin, “Analog Integrated Circuit Design,” 2nd edition, J. Wiley & Sons, 2011.
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Journal Publications

L. Wang, M. LaCroix, A. Chan Carusone, “A 4GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16nm FinFET,” IEEE Transactions on Circuits and Systems II, 2017. [On IEEExplore]

S. Chen, L. Wang, H. Zhang, R. Murugesu, D. Dunwell, A. Chan Carusone, “All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters,” IEEE Transactions on VLSI Systems, 2017. [On IEEExplore]

H. Zhang, X. Liu, J. Zhang, H. Zhang, J. Li, R. Zhang, S. Chen, A. Chan Carusone, “A Nano-Watt MOS-Only Voltage Reference with High-Slope PTAT Voltage Generators,” IEEE Transactions on Circuits and Systems II, 2017. [PDF Format]

S. Shahramian, B. Dehlaghi, A.Chan Carusone, “Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5us,” IEEE Journal of Solid-State Circuits, pp. 3192-3203, Nov 2016. [On IEEExplore]

A. Sharif-Bakhtiar, A.Chan Carusone, “A 20 Gb/s CMOS Optical Receiver with Limited-Bandwidth Front End and Local Feedback IIR-DFE,” IEEE Journal of Solid-State Circuits, pp. 2679-2689, Nov 2016. [On IEEExplore]

B. Dehlaghi, A.Chan Carusone, “A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication,” IEEE Journal of Solid-State Circuits, pp. 2690-2701, Nov 2016. [On IEEExplore]

V. Kozlov, A.Chan Carusone, “Capacitively-Coupled CMOS VCSEL Driver Circuits,” IEEE Journal of Solid-State Circuits, pp. 2077-2090, Sept 2016. [On IEEExplore]

S. Shahramian, A.Chan Carusone, “A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS,” IEEE Journal of Solid-State Circuits, pp. 1722-1735, July 2015. [PDF Format]

A. Samarah, A.Chan Carusone, “A Digital Phase-Locked Loop with Calibrated Coarse and Stochastic Fine TDC,” IEEE Journal of Solid-State Circuits, pp. 1829-1841, August 2013. [PDF Format]

D. Dunwell, A. Chan Carusone, “Modeling Oscillator Injection Locking Using the Phase Domain Response,” IEEE Transactions on Circuits and Systems I, 2013, pp. 2823-2833, November 2013. [PDF Format]

K. Yamamoto, A. Chan Carusone, “A 1-1-1-1 MASH Delta-Sigma Modulator with Dynamic Comparator-Based OTAs,” IEEE Journal of Solid-State Circuits, vol. 49, no. 8, pp. 1866-1883, August 2012. (IEEExplore Top 100 Download) (Journal of Solid-State Circuits Top 10 Download) [PDF Format]

S. Shahramian, H. Yasotharan, A. Chan Carusone, “Decision Feedback Equalizer Architectures with Multiple Continuous-time Infinite Impulse Response Filters,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 6, pp. 326-330, June 2012. (Transactions on Circuits and Systems II Top 25 Download) [PDF Format]

A. Chan Carusone, H. Yasotharan, T. Kao, “CMOS Technology Scaling Considerations for Multi Gbps Optical Receivers with Integrated Photodetectors,” IEEE Journal of Solid-State Circuits, vol.46, no.8, pp.1832-1842, August 2011. (Journal of Solid-State Circuits Top 25 Download) [PDF Format]

M. Hossain, A. Chan Carusone, “7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS,” IEEE Journal of Solid-State Circuits, vol.46, no.6, pp.1337-1348, June 2011. [PDF Format]

S. Shahramian, A. Hart, A. Tomkins, A. Chan Carusone, P. Garcia, P. Chevalier, S. Voinigescu, “Design of a Dual W- and D-Band PLL,” IEEE Journal of Solid-State Circuits, pp. 1011-1022, May 2011. (Journal of Solid-State Circuits Top 20 Download, April 2011) [PDF Format]

T. Shuo-Chun Kao, F. A. Musa and A. Chan Carusone “A 5-Gbps CMOS Optical Receiver with Integrated Spatially Modulated Light Detector and Equalization” IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 2844 – 2857, November 2010. [PDF Format]

M. Hossain and A. Chan Carusone, “10 Gb/s 70mW Burst Mode AC Coupled Receiver in 90nm CMOS,”IEEE Journal of Solid-State Circuits, pp. 524-537, March 2010.  [PDF Format]

M. Hossain and A. Chan Carusone, “Multi-Gb/s Bit-by-Bit Receiver Architectures for 1-D Partial Response Channels,”IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 270-279, January 2010.  [PDF Format]

M. Hossain and A. Chan Carusone, “CMOS Oscillators for Clock Distribution and Injection-Locked Deskew,”IEEE Journal of Solid-State Circuits, pp. 2138-2153, August 2009. (Journal of Solid-State Circuits Top 10 Download, August 2009) (IEEExplore Top 100 Download, August 2009) [PDF Format]

H. Cheng, F. A. Musa, and A. Chan Carusone, “A 32/16 Gb/s Dual-Mode Pulse Width Modulation Pre-emphasis (PWM-PE) Transmitter with 30-dB Loss Compensation using a High-Speed CML Design Methodology,”IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 1794-1806, August 2009. [PDF Format]

S. Shahramian, S. P. Voinigescu, A. Chan Carusone, “A 35-GS/s, 4-bit Flash ADC with Active Data and Clock Distribution Trees,”IEEE Journal of Solid-State Circuits, pp. 1709-1720, June 2009. (Journal of Solid-State Circuits Top 10 Download, June 2009) (IEEExplore Top 100 Download, June 2009) [PDF Format]

M. Bichan, M. Hossain, A. Chan Carusone, “Frequency-Division Bidirectional Communication over Chip-to-chip Channels,” IEEE Transactions on Advanced Packaging, Special Issue on High-Speed I/O Channels, pp. 298-305, May 2009. [PDF Format]

G. Ng, F. A. Musa, A. Chan Carusone, “A 2-Tap Traveling Wave Infinite Impulse Response (IIR) Filter with 12 dB Peaking at 24-GHz,”Electronics Letters, pp. 463-464, April 2009. [PDF Format]

J. Pham and A. Chan Carusone, “A Time-Interleaved Delta-Sigma-DAC Architecture Clocked at the Nyquist Rate,”IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 858-862, Sept. 2008. [PDF Format]

K. Yamamoto, A. Chan Carusone, and F. Dawson, “A Delta-Sigma Modulator with a Widely Programmable Center Frequency and 82-dB Peak SNDR,” IEEE Journal of Solid-State Circuits, pp. 1772-1782, Aug. 2008. [PDF Format]

A. Darabiha, A. Chan Carusone, and F. Kschischang, “Power Reduction Techniques for LDPC Decoders,”IEEE Journal of Solid-State Circuits, pp. 1835-1845, Aug. 2008. [PDF Format]

A. Darabiha, A. Chan Carusone, and F. Kschischang, “Block-Interlaced LDPC Decoders with Reduced Interconnect Complexity,”IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 74-78, January 2008. [PDF Format]

F. Musa and A. Chan Carusone, “Modeling and Design of Multilevel Bang-Bang CDRs in the Presence of ISI and Noise,”IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 2137-2147, October 2007. [PDF Format]

F. Musa, A. Chan Carusone, “A Baud-Rate Timing Recovery Scheme with a Dual-Function Analog Filter, ” IEEE Transactions on Circuits and Systems II, pp. 1393-1397, December 2006.  [PDF Format]

A. Garg, A. Chan Carusone, S. Voinigescu, “A 1-Tap 40-Gbps Look-ahead Decision Feedback Equalizer in 0.18μm SiGe BiCMOS Technology,”IEEE Journal of Solid-State Circuits, pp.2224-2232, October 2006. [PDF Format]

S. Shahramian, A. Chan Carusone, S. Voinigescu, “Design Methodology for a 40-GSamples/Sec Track & Hold Amplifier in 0.18-μm SiGe BiCMOS Technology,” IEEE Journal of Solid-State Circuits, pp. 2233-2240, October 2006. [PDF Format]

A. Chan Carusone, “An Equalizer Adaptation Algorithm to Reduce Jitter in Binary Receivers,” IEEE Transactions on Circuits and Systems II, pp. 807-811, September 2006. [PDF Format]

J. Sewter and A. Chan Carusone, “A 3-Tap FIR Filter with Cascaded Distributed Tap Amplifiers for Equalization up to 40 Gb/s in 0.18-mm CMOS,” IEEE Journal of Solid-State Circuits, pp. 1919-1929, August 2006. [PDF Format]

J. Sewter and A. Chan Carusone, “A CMOS Finite Impulse Response Filter with a Crossover Traveling Wave Topology for Equalization up to 30 Gb/s,” IEEE Journal of Solid-State Circuits, pp. 909-917, April 2006. [PDF Format]

J. Sewter and A. Chan Carusone, “Equalizer Architectures for 40-Gb/s Optical Systems Limited by Polarization-Mode Dispersion,” International Journal of High Speed Electronics and Systems, pp. 549-566, Sept. 2005. [PDF Format]

A. Chan Carusone and D. A. Johns, “Digital LMS Adaptation of Analog Filters Without Gradient Information,” IEEE Transactions on Circuits and Systems II, pp. 539-552, Aug. 2003. [PDF Format]

A. Carusone, K. Farzan and D. A. Johns, “Differential Signaling with a Reduced Number of Signal Paths,” IEEE Transactions on Circuits and Systems II, March 2001, pp. 294-300. [PDF Format]

A. Carusone and D. A. Johns, “Analogue Adaptive Filters – Past and Present,” IEE Transactions on Circuits, Systems, and Devices, February 2000, pp. 82-90. [PDF Format]

Magazine Articles

A. Chan Carusone, “Introduction to Digital I/O,”IEEE Solid-State Circuits Magazine, pp. 14-22, 4th Quarter, 2015. [Link]

A. Chan Carusone, “The Limits of Light: The finite bandwidth of optical fibre,”IEEE Circuits and Systems Magazine, pp. 55-63, 2nd Quarter, 2008. [PDF Format]

Book Chapters

A. Chan Carusone, F. Musa, J. Sewter, and G. Ng, “Integrated Circuits for Dispersion Compensation in Optical Communication Links,”  in Wireless and Optical Next Generation Communication Links, Editor K. Iniewski, J. Wiley & Sons, 2010.

Circuits at the Nanoscale A. Chan Carusone, “Equalization and Multilevel Modulation for Multi-Gbps Chip-to-chip Links,” in Circuits at the Nanoscale: Communications, Imaging, and Sensing, Editor K. Iniewski, CRC Press, 2008.
J. Sewter and A. Chan Carusone, “Equalizer Architectures for 40-Gb/s Optical Systems Limited by Polarization-Mode Dispersion,”  High-Speed Optical Tranceivers, Editors Y. Liu & H. Yang, World Scientific Press, 2006.

A. Carusone and D. A. Johns, “Analogue Adaptive Filters,” in Integrated Analogue Filter Design, Editor Y. Sun, IEE Press, 2002.

Conference Publications

Q. Wang, A. Liscidini, A. Chan Carusone, “Filtering ADCs for Wireless Receivers: a Survey,” Midwest Symposium on Circuits and Systems, Boston, Massachusetts, August 2017.

A. Sharif-Bakhtiar, M. G. Lee, A. Chan Carusone, “A 40-Gbps 0.5-pJ/bit VCSEL Driver in 28nm CMOS with Complex Zero Equalizer,” Custom Integrated Circuits Conference, Austin, Texas, May 2017. [PDF Format]

A. Sharif-Bakhtiar, M. G. Lee, A. Chan Carusone, “Low-Power CMOS Receivers for Short Reach Optical Communication,” Custom Integrated Circuits Conference, Austin, Texas, May 2017. [PDF Format]

Q. Wang, H. Shibata, A. Chan Carusone, A. Liscidini, “A LTE RX Front-end with Digitally Programmable Multi-Band Blocker Cancellation in 28nm CMOS,” Custom Integrated Circuits Conference, Austin, Texas, May 2017. [PDF Format]

L. Wang, M.A. LaCroix, A. Chan Carusone, “A 4GS/s Reconfigurable Folding Flash ADC for Time Interleaving in 16nm FinFET,” International Symposium on Circuits and Systems, Baltimore, Maryland, May 2017.

K. Banovic, A. Chan Carusone, “A Sub-mW Spectrum Sensing Architecture for Portable IEEE 802.22 Cognitive Radio Applications,” International Symposium on Circuits and Systems, Baltimore, Maryland, May 2017. [PDF Format]

B. Dehlaghi, R. Beerkens, D. Tonietto, A. Chan Carusone, “Interconnect Technologies for Terabit-per-second Die-to-Die Interfaces,” Compound Semiconductor Integrated Circuits Symposium, Austin, Texas, October 2016. [PDF Format]

A. Chan Carusone, B. Dehlaghi, R. Beerkens, D. Tonietto, “Ultra-Short-Reach Interconnects for Package-Level Integration,” Optical Interconnects Conference, San Diego, California, June 2016. [PDF Format]

S. Shahramian, B. Dehlaghi, A. Chan Carusone, “A 16 Gb/s 1 IIR + 1 DT DFE Compensating 28dB Loss with Edge-Based Adaptation Converging in 5us,” International Solid-State Circuits Conference, San Francisco, California, February 2016. [PDF Format]

V. Kozlov, A. Chan Carusone, “A 15Gb/s AC-coupled VCSEL Driver with Waveform Shaping in 65nm CMOS,” Compound Semiconductor IC Symposium, New Orleans, Louisiana, October 2015. [PDF Format]

B. Dehlaghi, A. Chan Carusone, “A 20 Gb/s 0.3 pJ/b Single-Ended Die-to-Die Transceiver in 28nm SOI CMOS,” Custom Integrated Circuits Conference, San Jose, California, 2015. [PDF Format]

A. Sharif-Bakhtiar, A. Chan Carusone, “A 19.6-Gbps CMOS Optical Receiver with Local Feedback IIR DFE,” VLSI Circuits Symposium, Kobe, Japan, June 2015. [PDF Format]

A. Samarah, A. Chan Carusone, “Cycle-Slipping Pull-In Range of Bang-Bang PLLs,” IEEE NEW Circuits and Systems Conference (NEwCAS), Grenoble, France, June 2015. [PDF Format]

A. Samarah, A. Chan Carusone, “Multi-Phase Bang-Bang Digital Phase Lock Loop,” IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, May 2015. [PDF Format]

M. Shibata, A. Chan Carusone, “A 26-Gb/s 1.80-pJ/b CMOS-Driven Transmitter for 850-nm Common-Cathode VCSELs,” Optical Fiber Conference (OFC), Los Angeles, California, March 2015. [PDF Format]

S. Shahramian, A. Chan Carusone, “A 10Gb/s 4.1mW 2-IIR + 1-Discrete-Tap DFE in 28nm LP CMOS,” European Solid-State Circuits Conference, Venice, Italy, 2014. [PDF Format]

L. Wang, Q. Wang, A. Chan Carusone, “Time Interleaved C-2C SAR ADC with Background Timing Skew Calibration in 65nm CMOS,” European Solid-State Circuits Conference, Venice, Italy, 2014. [PDF Format]

M. Bichan, D. Dunwell, Q. Wang, A. Chan Carusone, “A Passive Resonant Clocking Network for Distribution of a 2.5-GHz Clock in a Flash ADC,” IEEE International Symposium on Circuits and Systems, Melbourne, Australia, May 2014. [PDF Format]

D. Dunwell, A. Chan Carusone, “Channel Characterization Using Jitter Measurements,” IEEE International Symposium on Circuits and Systems, Beijing, China, May 2013. [PDF Format]

A. Sharif-Bakhtiar, S. Shahramian, A. Rousson, H. Yasotharan, A. Chan Carusone, “Integrated Photodiode Characterization in a SiGe BiCMOS Process,” IEEE Photonics Society 2nd Optical Interconnects Conference, Santa Fe, New Mexico, May 2013. [PDF Format]

A. Samarah, A. Chan Carusone, “A dead-zone free and linearized digital PLL,” International Conference on Electronics, Circuits, and Systems, Seville, Spain, December 2012. [PDF Format]

K. Banovic, A. Chan Carusone, “A 1.55mW Mixed-Signal Integrating Mixer for Direct Spectrum Estimation in 0.13um CMOS,” Asian Solid-State Circuits Conference, Kobe, Japan, November, 2012.

[PDF Format]

A. Samarah, A. Chan Carusone, “A Digital Phase-Locked Loop with Calibrated Coarse and Stochastic Fine TDC,” Custom Integrated Circuits Conference, San Jose, California, September 2012. [PDF Format]

D. Dunwell, A. Chan Carusone, J. Zerbe, B. Leibowitz, B. Daly, J. Eble, “A 2.3-4 GHz Injection-Locked Clock Multiplier with 55.7% Lock Range and 10-ns Power-On,” Custom Integrated Circuits Conference, San Jose, California, September 2012. [PDF Format]

A. Rousson, A. Chan Carusone, “A Multi-Lane Optical Receiver with Integrated Photodiodes in 90nm Standard CMOS,” Optical Fiber Conference (OFC), Los Angeles, California, March 2012. [PDF Format]

K. Yamamoto, A. Chan Carusone, “A 1-1-1-1 MASH Delta-Sigma Modulator Using Dynamic Comparator-Based OTAs,” Custom Integrated Circuits Conference, San Jose, California, September 2011. (Best Student Paper Award)  [PDF Format]

J. Zerbe, B. Daly, W. Dettloff, T. Stone, W. Stonecypher, P. Venkatesan, K. Prabhu, B. Su, J. Ren, B. Tsang, B. Leibowitz, D. Dunwell, A. Chan Carusone, J. Eble, “A 5.6Gb/s 2.4mW/Gb/s Bidirectional Link With 8ns Power-On,” VLSI Circuits Symposium, Kyoto, Japan, June 2011.

D. Dunwell, A. Chan Carusone, “Gain and Equalization Adaptation to Optimize the Vertical Eye Opening in a Wireline Receiver,” Custom Integrated Circuits Conference, San Jose, California, September 2010. [PDF Format] [PDF Format, slides]

A. Chan Carusone, H. Yasotharan, T. Kao, “Progress and Trends in Multi-Gbps Optical Receivers with CMOS Integrated Photodetectors,” Custom Integrated Circuits Conference, San Jose, California, September 2010. (Best Invited Paper Award)  [PDF Format]

D. Dunwell, A. Chan Carusone, “A 15-Gb/s Preamplifier with 10-dB Gain Control and 8-mV Sensitivity in 65-nm CMOS,” IEEE International Symposium on Circuits and Systems, Paris, France, June 2010. [PDF Format] [PDF Format, slides]

S. Shahramian, A. Hart, A. Chan Carusone, P. Garcia, P. Chevalier, S.P. Voinigescu, “A D-band PLL covering the 81-82 GHz, 86-92 GHz and 162-164 GHz bands,” IEEE IEEE RFIC Symposium, Anaheim, California, May 2010. [PDF Format]

M. Hossain, A. Chan Carusone, “A 6.8mW 7.4Gb/s Clock-Forwarded Receiver with up to 300MHz Jitter Tracking in 65nm CMOS,” International Solid-State Circuits Conference, San Francisco, California, February 2010. [PDF Format]

H. Yasotharan, A. Chan Carusone, “A Flexible Hardware Encoder for Systematic Low-Density Parity-Check Codes,”Midwest Symposium on Circuits and Systems, Cancun, Mexico, Aug 2009. [PDF Format]

M. Bichan, A. Chan Carusone, “The Effect of Redundancy on the Area-Offset Tradeoff in Dynamic Comparators,” Progress in Research in Microelectronics (PRIME) Conference, Cork, Ireland, July 2009. [PDF Format]

T. Shuo-Chun Kao and A. Chan Carusone, “A 5-Gbps Optical Receiver with Monolithically Integrated Photodetector in 0.18-um CMOS,”IEEE RFIC Symposium, Boston, MA, June 2009. [PDF Format]

A. Chan Carusone and F. Maloberti, “Multi-Rate Delta-Sigma Modulators,”to appear in the International Symposium on Circuits and Systems, Taipei, Taiwan, May 2009. [PDF Format], [PDF Format, slides]

P. Park, A. Chan Carusone, “A 20-Gb/s Coaxial Cable Receiver Analog Front-End in 90-nm CMOS Technology,”IEEE Asian Solid-State Circuits Conference, Fukuoka, Japan, November 2008. [PDF Format], [PDF Format, slides]

S. Shahramian, A. Chan Carusone, P. Schvan and S. P. Voinigescu, “An 81Gb/s, 1.2V TIALA-Retimer in 65nm GP CMOS Process,”Compound Semiconductor IC Symposium, Monterey, California, October, 2008. [PDF Format], [PDF Format, slides]

H. Cheng, A. Chan Carusone, “A 32/16 Gb/s 4/2-PAM Transmitter with PWM Pre-Emphasis and 1.2 Vpp per side Output Swing in 0.13-um CMOS,” Custom Integrated Circuits Conference, San Jose, California, September 2008. [PDF Format]

M. Hossain, A. Chan Carusone, “20 GHz Low Power QVCO and De-skew Techniques in 0.13-um Digital CMOS,”Custom Integrated Circuits Conference, San Jose, California, September 2008.  (Best Student Paper Award)  [PDF Format], [PDF Format, slides]

M. Bichan, A. Chan Carusone, “A 6.5 Gb/s Backplane Transmitter with 6-tap FIR Equalizer and Variable Tap Spacing,”Custom Integrated Circuits Conference, San Jose, California, September 2008. [PDF Format]

G. Ng, A. Chan Carusone, “A 38-Gb/s 2-tap Transversal Equalizer in 0.13-um CMOS using a Microstrip Delay Element,” IEEE RFIC Symposium, Atlanta, George, June 2008. [PDF Format], [PDF Format, slides]

F. Musa, A. Chan Carusone, “A Passive Filter Aided Timing Recovery Scheme,” IEEE Int. Symp. Circuits and Syst., May 2008. [PDF Format], [PDF Format, slides]

K. Yamamoto, A. Chan Carusone, and F. Dawson, “A Delta-Sigma Modulator with a Widely Programmable Center Frequency and 82-dB Peak SNDR,” Custom Integrated Circuits Conference, San Jose, California, September 2007.  (Best Student Paper Award)  [PDF Format], [PDF Format, slides]

A. Darabiha, A. Chan Carusone, and F. Kschischang, “A 3.3-Gbps Bit-Serial Block-Interlaced Min-Sum LDPC Decoder in 0.13-um CMOS,” Custom Integrated Circuits Conference, San Jose, California, September 2007. [PDF Format]

A. Chan Carusone, “Practical Challenges for Electronic Dispersion Compensation in CMOS,” LEOS Summer Topical Meeting, Portland, Oregon, July 2007. [PDF Format], [PDF Format, slides].

M. Hossain and A. Chan Carusone, “A 14-Gb/s 32 mW AC coupled receiver in 90-nm CMOS,” VLSI Circuits Symposium, Kyoto, Japan, June 2007. [PDF Format], [PDF Format, slides]

M. Bichan, A. Chan Carusone, “Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links,”IEEE Int. Symp. Circuits and Syst., New Orleans, Louisiana, May 2007. [PDF Format], [PDF Format, slides]

G. Ng, A. Chan Carusone, “Electronic Dispersion Compensation of 40-Gb/s Multimode Fiber Links Using IIR Equalization,” 2007 Optical Fiber Conference (OFC), Anaheim, CA. [PDF Format], [PDF Format Slides]

S.P. Voinigescu, T. Chalvatzis, K.H.K. Yau, A. Hazneci, A. Garg, S. Shahramian, T. Yao, M. Gordon, T.O. Dickson, E. Laskin, S.T. Nicolson, A. Chan Carusone, L. Tchoketch-Kebir, O. Yuryevich, G. Ng, B. Lai, and P.Liu, “SiGe BiCMOS for Analog, High-Speed Digital and Millimetre-Wave Applications Beyond 50 GHz,” IEEE Bipolar / BiCMOS Circuits and Technology Meeting, Maastricht, The Netherlands, October 2006. [PDF Format],

M. Hossain and A. Chan Carusone, “A 19-GHz Broadband Amplifier Using a gm-Boosted Cascode in 0.18-μm CMOS,” Custom Integrated Circuits Conference, San Jose, California, September 2006. [PDF Format], [PDF Format, Slides]

S. Shahramian, S. P. Voinigescu and A. Chan Carusone, “A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology,” Custom Integrated Circuits Conference, San Jose, California, September 2006. [PDF Format], [PDF Format, Slides]

A. Darabiha, A. Chan Carusone and F. R. Kschischang, “A Bit-Serial Approximate Min-Sum LDPC Decoder and FPGA Implementation,” IEEE Int. Symp. Circuits and Syst., May 2006. [PDF Format], [PDF Format, Slides]

S. Shahramian, A. Chan Carusone, S. P. Voinigescu, “A 40-GSamples/Sec Track & Hold Amplifier in 0.18μm SiGe BiCMOS Technology,” Compound Semiconductor Integrated Circuits Symposium, Palm Springs, California, October 2005.  (Best Paper Award)  [PDF Format]

A. Garg, A. Chan Carusone, S. P. Voinigescu, “A 1-Tap 40-Gbps Lookahead Decision Feedback Equalizer in 0.18μm SiGe BiCMOS Technology,”Compound Semiconductor Integrated Circuits Symposium, Palm Springs, California, October 2005.  [PDF Format]

J. Sewter and A. Chan Carusone, “A 40 Gb/s Transversal Filter in 0.18 μm CMOS Using Distributed Amplifiers,”Custom Integrated Circuits Conference, San Jose, California, September 2005.  [PDF Format], [PDF Format, Slides]

J. Sewter and A. Chan Carusone, “A 3-Tap Digitally Programmable Transversal Filter in 90 nm CMOS for Equalization up to 30 Gb/s,”Symposium on VLSI Circuits, June 2005. [PDF Format], [PDF Format, Slides]

J. Sewter and A. Chan Carusone, “A Comparison of Equalizers for Compensating Polarization-Mode Dispersion in 40-Gb/s Optical Systems,”  IEEE Int. Symp. Circuits and Syst., May 2005. [PDF Format], [PDF Format, Slides]

A. Chan Carusone, “Jitter Equalization for Binary Baseband Communication,”  IEEE Int. Symp. Circuits and Syst., May 2005. [PDF Format], [PDF Format, Slides]

A. Darabiha, A. Chan Carusone and F. R. Kschischang, “Multi-Gbit/sec Low Density Parity Check Decoders with Reduced Interconnect Complexity,” IEEE Int. Symp. Circuits and Syst., May 2005. [PDF Format], [PDF Format, Slides]

S. Shahramian and A. Chan Carusone, “Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization,” IEEE Int. Symp. Circuits and Syst., May 2004. [PDF Format]

F. Musa and A. Chan Carusone, “Clock recovery in high-speed multilevel serial links,” IEEE Int. Symp. Circuits and Syst., May 2003. [PDF Format], [PDF Format, Slides]

A. Chan Carusone, “Analog Adaptive Filters,” tutorial at the IEEE Int. Symp. Circuits and Syst., Bangkok, Thailand, May 2003. [PDF Format, Slides]

D. Daly and A. Chan Carusone, “A sigma-delta based open loop frequency modulator,” IEEE Int. Symp. Circuits and Syst., May 2003. [PDF Format], [PDF Format, Poster]

A. Chan Carusone and D. A. Johns, “Analog Filter Adaptation Using a Dithered Linear Search Algorithm,” IEEE Int. Symp. Circuits and Syst., May 2002. [PDF Format], [PDF Format, Slides]

A. Chan Carusone and D. A. Johns, “A 5th Order Gm-C Filer in 0.25 um CMOS with Digitally Programmable Poles & Zeroes,” IEEE Int. Symp. Circuits and Syst., May 2002. [PDF Format], [PDF Format, Slides]

A. Carusone and D. A. Johns, “Obtaining Digital Gradient Signals for Analog Adaptive Filters,” IEEE Int. Symp. Circuits and Syst., May 1999. [PDF Format], [PDF Format, Slides]

Ph. D. Thesis

A. Chan Carusone, Digital Algorithms for Analog Adaptive Filters, Feb. 2002. [PDF Format].