IC Design Gallery

4GS/s Reconfigurable ADC in 16nm FinFET

Designer: Luke Wang

Technology: 16nm FinFET CMOS

This ADC with VGA is implemented in 16nm FinFET technology and has a resolution programmable from 2 to 6 bits while maintaining state-of-the-art power efficiency.

L. Wang, M.A. LaCroix, A. Chan Carusone, “A 4GS/s Reconfigurable Folding Flash ADC for Time Interleaving in 16nm FinFET,” International Symposium on Circuits and Systems, Baltimore, Maryland, May 2017.


16Gb/s Wireline Receiver  with Adaptive 1 IIR + 1 Discrete-Time Tap DFE

Designers: Shayan Shahramian, Behzad Dehlaghi

Technology: 28nm FDSOI CMOS

This receiver is the first to demonstrate a practical and fast adaptation method (converging in 5us) for decision feedback equalizers combining IIR and discrete-time taps.

S. Shahramian, B. Dehlaghi, A.Chan Carusone, “Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5us,” IEEE Journal of Solid-State Circuits, pp. 3192-3203, Nov 2016. [On IEEExplore]

shahramian_28nmsoi
20Gb/s Receiver for Short-Reach Parallel Optical Communication

Designer: Alireza Sharif-Bakhtiar

Technology: 65nm CMOS

An ultra-low-power technique for IIR decision feedback equalization enables 20Gb/s operation consuming only 0.3pJ/bit

A. Sharif-Bakhtiar, A.Chan Carusone, “A 20 Gb/s CMOS Optical Receiver with Limited-Bandwidth Front End and Local Feedback IIR-DFE,” IEEE Journal of Solid-State Circuits, pp. 2679-2689, Nov 2016. [On IEEExplore]

sharifbakhtiar_iirdfe
20Gb/s/wire Parallel Interface 

Designer: Behzad Dehlaghi

Technology: 28nm FDSOI CMOS

This receiver establishes a new benchmark for density by combining ultra-compact transceivers consuming only 0.3pJ/bit and a custom-designed silicon interposer.

B. Dehlaghi, A.Chan Carusone, “A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication,” IEEE Journal of Solid-State Circuits, pp. 2690-2701, Nov 2016. [On IEEExplore]

dehlaghi_dietodie
AC-Coupled Laser Diode Driver

Designer: Victor Kozlov

Technology: 65nm CMOS

By demonstrating a laser driver with capacitive AC coupling integrated on-die into a compact area, this design paves the way for the future use of optical I/O in nanoscale CMOS ASICs.

V. Kozlov, A.Chan Carusone, “Capacitively-Coupled CMOS VCSEL Driver Circuits,” IEEE Journal of Solid-State Circuits, pp. 2077-2090, Sept 2016. [On IEEExplore]

kozlov_ldd
Receiver with Hybrid 2-IIR + 1-Discrete-Time Tap DFE

Designer: Shayan Shahramian

Technology: 28nm LP CMOS

This is the first receiver to combine IIR and discrete-time DFE taps into a single receiver, demonstrating an excellent combination of performance and power considering the LP technology used.

S. Shahramian, A.Chan Carusone, “A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS,” IEEE Journal of Solid-State Circuits, pp. 1722-1735, July 2015. [PDF Format]

shahramian_28nmlp
26 Gb/s Laser Diode Driver

Designer: Masumi Shibata

Technology: 65nm CMOS

This optical transmitter operates at speeds usually reserved for BiCMOS technologies.  It demonstrates that very low power consumption is possible using CMOS circuits and inexpensive packaging.

M. Shibata, A. Chan Carusone, “A 26-Gb/s 1.80-pJ/b CMOS-Driven Transmitter for 850-nm Common-Cathode VCSELs,” Optical Fiber Conference (OFC), Los Angeles, California, March 2015. [PDF Format]

shibata_ldd
A 2 – 2.5GHz All-Digital PLL

Designer: Amer Samarah

Technology: 130-nm CMOS

A 2–2.5-GHz digital phase-locked loop (DPLL) in 0.13-um
CMOS consuming a total of 15.2 mW with a novel stochastic time-to-digital converter.  Random jitter as low as 213fs-rms was measured.

A. Samarah, A.Chan Carusone, “A Digital Phase-Locked Loop with Calibrated Coarse and Stochastic Fine TDC,” IEEE Journal of Solid-State Circuits, pp. 1829-1841 August 2013. [PDF Format]

Samara_DPLL_die_photo
A MASH 1-1-1-1 Delta-Sigma Modulator

Designer: Kentaro Yamamoto

Technology: 65-nm CMOS

The 65-nm CMOS prototype achieves a 70.4 dB peak SNDR over a 2.5-MHz bandwidth while consuming 3.73 mW from a 1.2-V supply. The 276-fJ/conv-step FoM represents a four times improvement over previously-reported delta-sigma modulators using similar zero-crossing-based circuits.

K. Yamamoto, A. Chan Carusone, “A 1-1-1-1 MASH Delta-Sigma Modulator with Dynamic Comparator-Based OTAs,”IEEE Journal of Solid-State Circuits, vol. 49, no. 8, pp. 1866-1883, August 2012. [PDF Format]

MASH_1-1-1-1_die_photo
A 2.3-4 GHz Injection-Locked Clock Multiplier

Designer: Dustin Dunwell

Technology: 65-nm CMOS

A frequency-agile multiplying injection-locked oscillator (MILO) suitable for fast power cycling achieves lock over a range of 55.7% around the 3.16-GHz center frequency within 10 reference clock cycles.

D. Dunwell, A. Chan Carusone, J. Zerbe, B. Leibowitz, B. Daly, J. Eble, “A 2.3-4 GHz Injection-Locked Clock Multiplier with 55.7% Lock Range and 10-ns Power-On,” Custom Integrated Circuits Conference, San Jose, California, September 2012. [PDF Format]

Dunwell_MILO_die_photo
A 7.4 Gb/s 6.8 mW Source Synchronous Receiver

Designer: Masum Hossain

Technology: 65-nm CMOS

This receiver can track very high-frequency jitter on a source-synchronous clock forwarded from a transmitter. Each receiver consumes 0.92 pJ/bit operating at 7.4 Gb/s and has a jitter tolerance of 1.5 UI at 200 MHz.

M. Hossain, A. Chan Carusone, “7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS,” IEEE Journal of Solid-State Circuits, vol.46, no.6, pp.1337-1348, June 2011. [PDF Format]

A 5-Gb/s Half-Rate Receiver for AC-Coupled Channels

Designer: Masum Hossain

Technology: 0.18-um CMOS

This receiver recovers data at up to 5 Gb/s from a channel that includes tiny 50-fF AC coupling capacitors. It provides dual half-rate outputs in spite of the fact that no clock recovery is performed.

M. Hossain and A. Chan Carusone, “Multi-Gb/s Bit-by-Bit Receiver Architectures for 1-D Partial Response Channels,” IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 270-279, January 2010. [PDF Format]

Injection-Locked Quadrature Oscillators for GHz Clock AlignmentDesigner: Masum Hossain

Technology: 90-nm CMOS

This quadrature ring oscillator provides a 2 to 7 GHz clock with controllable phase while consuming 14 mW.

M. Hossain and A. Chan Carusone, “CMOS Oscillators for Clock Distribution and Injection-Locked Deskew,”IEEE Journal of Solid-State Circuits, pp. 2138-2153, August 2009. [PDF Format]

A 32-Gb/s 4-PAM Coaxial Cable Transmitter

Designer: Horace Cheng

Technology: 0.13-um CMOS

This is the fastest 4-PAM transmitter ever demonstrated to date.  It incorporates an equalizer capable of compensating for up to 30-dB of cable loss.

H. Cheng, F. A. Musa, and A. Chan Carusone, “A 32/16 Gb/s Dual-Mode Pulse Width Modulation Pre-emphasis (PWM-PE) Transmitter with 30-dB Loss Compensation using a High-Speed CML Design Methodology,” IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 1794 – 1806, August 2009. [PDF Format]

A 35-GS/s, 4-bit Flash ADC

Designer: Shahriar Shahramian

Technology: 0.18-um SiGe BiCMOS

This analog-to-digital converter has has 3.7 ENOB with an effective resolution bandwidth of 8-GHz at a full-scale input of only 270-mVpp differential.

S. Shahramian, S. P. Voinigescu, A. Chan Carusone, “A 35-GS/s, 4-bit Flash ADC with Active Data and Clock Distribution Trees,” IEEE Journal of Solid-State Circuits, pp. 1709-1720, June 2009. [PDF Format]

A 20-Gb/s Coaxial Cable Receiver

Designer: Peter Park

Technology: 90-nm CMOS

This analog front end incorporates a variable gain of up to 31dB and an equalizer with sufficient bandwidth for 20Gb/s data while consuming only 138-mW.

P. Park, A. Chan Carusone, “A 20-Gb/s Coaxial Cable Receiver Analog Front-End in 90-nm CMOS Technology,” IEEE Asian Solid-State Circuits Conference, Fukuoka, Japan, November 2008. [PDF Format]

A 40-Gbps 2-Tap Linear Equalizer

Designer: George Ng

Technology: 0.13-um CMOS

This equalizer consumes only 30-mW from a 1.2-V supply and is capable of compensating for channel losses of more than 14-dB at one-half the data rate.

G. Ng, A. Chan Carusone, “A 38-Gb/s 2-tap Transversal Equalizer in 0.13-um CMOS using a Microstrip Delay Element,” IEEE RFIC Symposium, Atlanta, George, June 2008. [PDF Format], [PDF Format, slides]

A 3.3-Gbps LDPC Decoder

Designer:  Ahmad Darabiha

Technology:  0.13-um CMOS

This is the fastest iterative error control decoder reported to date.  It is also capable of decoding with only 150 pJ/bit.

A. Darabiha, A. Chan Carusone, and F. Kschischang, “Power Reduction Techniques for LDPC Decoders,” IEEE Journal of Solid-State Circuits, pp. 1835 – 1845, Aug. 2008. [PDF Format]

Widely Programmable Bandpass DS Modulator

Designer:  Kentaro Yamamoto

Technology:  0.18-um CMOS

This design has a centre-frequency programmable from dc to 0.3fs and a peak SNDR of 82 dB.

K. Yamamoto, A. Chan Carusone, and F. Dawson, “A Delta-Sigma Modulator with a Widely Programmable Center Frequency and 82-dB Peak SNDR,” IEEE Journal of Solid-State Circuits, pp. 1772 – 1782, Aug. 2008. [PDF Format]

14-Gb/s AC-Coupled Receiver

Designer:  Masum Hossain

Technology:  90-nm CMOS

This is the highest-speed AC-coupled receiver reported to date with an integrated coupling capacitance below 100-fF.

M. Hossain and A. Chan Carusone, “A 14-Gb/s 32 mW AC coupled receiver in 90-nm CMOS,” VLSI Circuits Symposium, Kyoto, Japan, June 2007. [PDF Format]

19-GHz Broadband Amplifier

Designer:  Masum Hossain

Technology:  0.18-um CMOS

With a gain of 10-dB, this amplifier has the highest measured bandwidth of any amplifier (with the exception of distributed amplifiers) ever reported in this technology.

M. Hossain and A. Chan Carusone, “A 19-GHz Broadband Amplifier Using a gm-Boosted Cascode in 0.18-μm CMOS,” Custom Integrated Circuits Conference, San Jose, California, September 2006. [PDF Format]

30-GHz Track-and-Hold Amplifier

Designer:  Shahriar Shahramian

Technology:  0.13-um CMOS

With a 30-GHz clock frequency and 7-GHz bandwidth, this is the fastest track-and-hold amplifier ever reported in CMOS.  It has a measured THD of -29 dB.

S. Shahramian, S. P. Voinigescu and A. Chan Carusone, “A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology,” to appear at the Custom Integrated Circuits Conference, San Jose, California, September 2006. [PDF Format]

2-GHz CMOS Biquad Filter

Designer:  Faisal Musa

Technology:  0.18-um CMOS

This filter has a Q>3 and can be used for equalization and timing recovery at data rates above 3-Gb/s.

F. Musa, A. Chan Carusone, “A Baud-Rate Timing Recovery Scheme with a Dual-Function Analog Filter, ” IEEE Transactions on Circuits and Systems II, December 2006, pp. 1393-1397.  [PDF Format]

40-Gb/s 1-tap Decision Feedback Equalizer

Designer:  Adesh Garg

Technology:  SiGe BiCMOS

This is the fastest DFE ever reported, tested up to 40-Gb/s.  It occupies an area of 1.5mmX1mm and operates from a 3.3V supply with 230mA current.

A. Garg, A. Chan Carusone, S. Voinigescu, “A 1-Tap 40-Gbps Look-ahead Decision Feedback Equalizer in 0.18μm SiGe BiCMOS Technology,” IEEE Journal of Solid-State Circuits, October 2006, pp.2224-2232. [PDF Format]

40-Gb/s 3-tap Linear Equalizer

Designer:  Jonathan Sewter

Technology:  0.18-um CMOS

This is remains the fastest linear equalizer ever reported in any CMOS process.  It consumes 70 mW from a 1.8 V supply in an area 1 mm x 1 mm.

J. Sewter and A. Chan Carusone, “A 3-Tap FIR Filter with Cascaded Distributed Tap Amplifiers for Equalization up to 40 Gb/s in 0.18-mm CMOS,” IEEE Journal of Solid-State Circuits, August 2006, pp. 1919-1929. [PDF Format]

30-Gb/s 3-tap Digitally Programmable Linear Equalizer

Designer:  Jonathan Sewter

Technology:  90-nm CMOS

At the time of its publication, this was the fastest linear equalizer reported in any CMOS technology.  Consuming only 25 mW from a 1-V supply, and fitting into an area 0.3 mm2, the equalizer has a a serial digital interface to set the tap gains.

J. Sewter and A. Chan Carusone, “A CMOS Finite Impulse Response Filter with a Crossover Traveling Wave Topology for Equalization up to 30 Gb/s,” IEEE Journal of Solid-State Circuits, April 2006, pp. 909-917. [PDF Format]