Designer: Masum Hossain

Technology: 65-nm CMOS

This receiver can track very high-frequency jitter on a source-synchronous clock forwarded from a transmitter. Each receiver consumes 0.92 pJ/bit operating at 7.4 Gb/s and has a jitter tolerance of 1.5 UI at 200 MHz.

M. Hossain, A. Chan Carusone, “7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS,” IEEE Journal of Solid-State Circuits, vol.46, no.6, pp.1337-1348, June 2011. [PDF Format]

Designer: Masum Hossain

Technology: 0.18-um CMOS

This receiver recovers data at up to 5 Gb/s from a channel that includes tiny 50-fF AC coupling capacitors. It provides dual half-rate outputs in spite of the fact that no clock recovery is performed.

M. Hossain and A. Chan Carusone, “Multi-Gb/s Bit-by-Bit Receiver Architectures for 1-D Partial Response Channels,” IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 270-279, January 2010. [PDF Format]

Designer: Masum Hossain

Technology: 90-nm CMOS

This quadrature ring oscillator provides a 2 to 7 GHz clock with controllable phase while consuming 14 mW.

M. Hossain and A. Chan Carusone, “CMOS Oscillators for Clock Distribution and Injection-Locked Deskew,”IEEE Journal of Solid-State Circuits, pp. 2138-2153, August 2009. [PDF Format]

Designer: Horace Cheng

Technology: 0.13-um CMOS

This is the fastest 4-PAM transmitter ever demonstrated to date.  It incorporates an equalizer capable of compensating for up to 30-dB of cable loss.

H. Cheng, F. A. Musa, and A. Chan Carusone, “A 32/16 Gb/s Dual-Mode Pulse Width Modulation Pre-emphasis (PWM-PE) Transmitter with 30-dB Loss Compensation using a High-Speed CML Design Methodology,” IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 1794 – 1806, August 2009. [PDF Format]

Designer: Shahriar Shahramian

Technology: 0.18-um SiGe BiCMOS

This analog-to-digital converter has has 3.7 ENOB with an effective resolution bandwidth of 8-GHz at a full-scale input of only 270-mVpp differential.

S. Shahramian, S. P. Voinigescu, A. Chan Carusone, “A 35-GS/s, 4-bit Flash ADC with Active Data and Clock Distribution Trees,” IEEE Journal of Solid-State Circuits, pp. 1709-1720, June 2009. [PDF Format]

Designer: Peter Park

Technology: 90-nm CMOS

This analog front end incorporates a variable gain of up to 31dB and an equalizer with sufficient bandwidth for 20Gb/s data while consuming only 138-mW.

P. Park, A. Chan Carusone, “A 20-Gb/s Coaxial Cable Receiver Analog Front-End in 90-nm CMOS Technology,” IEEE Asian Solid-State Circuits Conference, Fukuoka, Japan, November 2008. [PDF Format]

Designer: George Ng

Technology: 0.13-um CMOS

This equalizer consumes only 30-mW from a 1.2-V supply and is capable of compensating for channel losses of more than 14-dB at one-half the data rate.

G. Ng, A. Chan Carusone, “A 38-Gb/s 2-tap Transversal Equalizer in 0.13-um CMOS using a Microstrip Delay Element,” IEEE RFIC Symposium, Atlanta, George, June 2008. [PDF Format], [PDF Format, slides]

Designer:  Ahmad Darabiha

Technology:  0.13-um CMOS

This is the fastest iterative error control decoder reported to date.  It is also capable of decoding with only 150 pJ/bit.

A. Darabiha, A. Chan Carusone, and F. Kschischang, “Power Reduction Techniques for LDPC Decoders,” IEEE Journal of Solid-State Circuits, pp. 1835 – 1845, Aug. 2008. [PDF Format]

Designer:  Kentaro Yamamoto

Technology:  0.18-um CMOS

This design has a centre-frequency programmable from dc to 0.3f_s and a peak SNDR of 82 dB.

K. Yamamoto, A. Chan Carusone, and F. Dawson, “A Delta-Sigma Modulator with a Widely Programmable Center Frequency and 82-dB Peak SNDR,” IEEE Journal of Solid-State Circuits, pp. 1772 – 1782, Aug. 2008. [PDF Format]

Designer:  Masum Hossain

Technology:  90-nm CMOS

This is the highest-speed AC-coupled receiver reported to date with an integrated coupling capacitance below 100-fF.

M. Hossain and A. Chan Carusone, “A 14-Gb/s 32 mW AC coupled receiver in 90-nm CMOS,” VLSI Circuits Symposium, Kyoto, Japan, June 2007. [PDF Format]

Designer:  Masum Hossain

Technology:  0.18-um CMOS

With a gain of 10-dB, this amplifier has the highest measured bandwidth of any amplifier (with the exception of distributed amplifiers) ever reported in this technology.

M. Hossain and A. Chan Carusone, “A 19-GHz Broadband Amplifier Using a gm-Boosted Cascode in 0.18-μm CMOS,” Custom Integrated Circuits Conference, San Jose, California, September 2006. [PDF Format]

Designer:  Shahriar Shahramian

Technology:  0.13-um CMOS

With a 30-GHz clock frequency and 7-GHz bandwidth, this is the fastest track-and-hold amplifier ever reported in CMOS.  It has a measured THD of -29 dB.

S. Shahramian, S. P. Voinigescu and A. Chan Carusone, “A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology,” to appear at the Custom Integrated Circuits Conference, San Jose, California, September 2006. [PDF Format]

Designer:  Faisal Musa

Technology:  0.18-um CMOS

This filter has a Q>3 and can be used for equalization and timing recovery at data rates above 3-Gb/s.

F. Musa, A. Chan Carusone, “A Baud-Rate Timing Recovery Scheme with a Dual-Function Analog Filter, ” IEEE Transactions on Circuits and Systems II, December 2006, pp. 1393-1397.  [PDF Format]

Designer:  Adesh Garg

Technology:  SiGe BiCMOS

This is the fastest DFE ever reported, tested up to 40-Gb/s.  It occupies an area of 1.5mmX1mm and operates from a 3.3V supply with 230mA current.

A. Garg, A. Chan Carusone, S. Voinigescu, “A 1-Tap 40-Gbps Look-ahead Decision Feedback Equalizer in 0.18μm SiGe BiCMOS Technology,” IEEE Journal of Solid-State Circuits, October 2006, pp.2224-2232. [PDF Format]

Designer:  Jonathan Sewter

Technology:  0.18-um CMOS

This is remains the fastest linear equalizer ever reported in any CMOS process.  It consumes 70 mW from a 1.8 V supply in an area 1 mm x 1 mm.

J. Sewter and A. Chan Carusone, “A 3-Tap FIR Filter with Cascaded Distributed Tap Amplifiers for Equalization up to 40 Gb/s in 0.18-mm CMOS,” IEEE Journal of Solid-State Circuits, August 2006, pp. 1919-1929. [PDF Format]

Designer:  Jonathan Sewter

Technology:  90-nm CMOS

At the time of its publication, this was the fastest linear equalizer reported in any CMOS technology.  Consuming only 25 mW from a 1-V supply, and fitting into an area 0.3 mm², the equalizer has a a serial digital interface to set the tap gains.

J. Sewter and A. Chan Carusone, “A CMOS Finite Impulse Response Filter with a Crossover Traveling Wave Topology for Equalization up to 30 Gb/s,” IEEE Journal of Solid-State Circuits, April 2006, pp. 909-917. [PDF Format]