Software-Defined Wireline Communication

This project enables the continued proliferation of broadband communication technology by integrating robust, reconfigurable, and efficient digital signal processing (DSP) into our highest speed communication links over copper wires and optical fibre. Multi-Gbps transceives generally rely upon analog signal processing to condition the communication waveforms, compensating for channel impairments and eliminating noise introduced along the way. Although DSP can offer the improvements in signal integrity needed for long channels and higher data rates, the associated power consumption can be excessive, especially when the channel happens to be short.  It is impractical to tailor different transceiver circuits for each of the hundreds of different channels that may arise in a network.  Hence, our vision is of reconfigurable transceiver circuits for wireline communication that leverage a flexible DSP and perform efficient communication at 100+ Gbps over a wide variety of channels [1,2] – a “software-defined” transceiver for our highest-speed communication links.

We have already demonstrated the analog front-end circuits, including high-speed data converters, needed for such links.  Since the analog circuits are being followed by a sophisticated DSP, digital calibration is a valuable tool in such systems, and a key part of our research.  The improvement offered by calibration is illustrated below [3].  Results from an ADC reconfigurable from 2- to 6-bits of resolution are also shown.  Further improvements have been demonstrated in [4].

Our work in this area employs nanoscale CMOS (including FinFET) VLSI fabrication technologies to make state-of-the-art contributions.

[1] L. Wang, Y. Fu, M. LaCroix, E. Chong, A. Chan Carusone, “A 64-Gb/s 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET,” IEEE Journal of Solid-State Circuits, Dec 2018. [PDF]

[2] L. Wang , Y. Fu , M. LaCroix , E. Chong , A. Chan Carusone, “A 64Gb/s PAM-4 Transceiver Utilizing an Adaptive Threshold ADC in 16nm FinFET,” International Solid-State Circuits Conference, Feb. 2018.

[3] L. Wang, M. LaCroix, A. Chan Carusone, “A 4GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16nm FinFET,” IEEE Transactions on Circuits and Systems II, Dec. 2017. [On IEEExplore]

[4] P. Chen, N. Wary, L. Wang, Q. Wang, A. Chan Carusone, “All-Digital Calibration Algorithms to Correct for Static Non-Linearities in ADCs,” IEEE International Symposium on Circuits and Systems, Seville, Spain, October 2020. [PDF] [YouTube]

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