This research thrust looks at the major challenge facing computer and networking systems now and for the next decade: interconnect energy efficiency. Aggregate interconnect input-output (I/O) bandwidth must increase aggressively to take full advantage of tomorrow’s highly parallel processors, but the total power available for I/O is constrained.
In particular, network data traffic patterns pose a difficult problem: how do we maintain energy efficiency in the presence of widely-varying bandwidth demands? No single strategy appears to offer the energy-efficiency improvements that will be required in the next decade. Rather, the entire system must be co-optimized including the channel, transmitter, receiver, and clocking circuits, with the objective function being energy consumption per communicated bit. This optimized system must then exploit a combination of power management techniques including burst-mode operation, low-power standby, dynamic voltage and frequency scaling, and dynamic link narrowing.
Our research looks at several possible solutions. For example, there are significant potential benefits for co-packaging dies to shorten the length of the links between them, as shown below. We have already demonstrated state-of-the-art energy efficiency and density over such ultra-short-reach (USR) die-to-die links .
However co-packaging multiple dies to shorten the length of a link will not always be possible.
The potential for impact is tremendous. Worldwide, 220 TWh per year of power goes into compute servers, and interface power is a very significant fraction of that, ranging from 10% – 25% depending upon the computing load present. A research result that can shave 1% off of the interface power alone (i.e. 0.1% of total server power), would provide a reduction in electricity consumption equivalent to 20,000 homes. We are currently exploring techniques that promise reductions much greater than 1%!
 B. Dehlaghi, A.Chan Carusone, “A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication,” IEEE Journal of Solid-State Circuits, pp. 2690-2701, Nov 2016. [On IEEExplore]