People

Prof. Tony Chan Carusone directs research at ISL.  Visit his personal profile or contact him at tony.chan.carusone@isl.utoronto.ca.

Current Graduate Students

Name: Ming Yang
Position: Ph.D. Candidate
Research: Signal Processing for Next Generation Wireline Communication
Contact: ming.yang@isl.utoronto.ca
Name: Wagih Ismail
Position: Ph.D. Candidate
Research: Broadband Wireless Receiver A/D Conversion
Contact: wagih.ismail@isl.utoronto.ca
Name: Foad Arvani
Position: Ph.D. Candidate
Research: Time-interleaved receiver front-ends
Contact: foad.arvani@isl.utoronto.ca
Name: Luke Wang
Position: Ph.D. Candidate
Research: Time-interleaved receiver front-ends
Contact: luke.wang@isl.utoronto.ca
Web Link
Name: Jeffrey Wang
Position: Ph.D. Candidate
Research:Mixed Analog-Digital Filters
Contact: jeffrey.wang@isl.utoronto.ca
Web Link
Name: Paul Chen
Position: M.A.Sc. Candidate
Research: A/D Conversion for Broadband Data Communication
Contact: paul.chen@isl.utoronto.ca
Name: Danial Mohammadi
Position: M.A.Sc. Candidate
Research: Wireless Receiver A/D Conversion
Contact: danial.mohammadi@isl.utoronto.ca
Name: Dhruv Patel
Position: M.A.Sc. Candidate
Research: CMOS Optical Receiver Circuits
Contact: dhruv.patel@isl.utoronto.ca
Name: Danny Zhang
Position: M.A.Sc. Candidate
Research: Highly Parallel Wireline Communication
Contact: danny.zhang@isl.utoronto.ca
Name: Durand Jarrett-Amor
Position: Ph.D. Candidate
Research: Highly Parallel Wireline Communication
Contact: durand.jarrettamor@isl.utoronto.ca
Name: Rudraneil Saha
Position: Ph.D. Candidate
Research: CMOS Broadband Wireless Communication Circuits
Contact: rudraneil.saha@isl.utoronto.ca
Name: Deng Pan
Position: M.A.Sc. Candidate
Research: Integrated Circuit Acceleration of Machine Learning
Contact: deng.pan@isl.utoronto.ca
Name: Behraz Vatankhahghadim
Position: Ph.D. Candidate
Research: Signal Processing for Next Generation Wireline Communication
Contact: behraz.vatankhahghadim@isl.utoronto.ca
Name: Xunjun Mo
Position: M.Eng. Candidate
Research: High-Speed Clocking Circuits in Nanoscale CMOS
Contact: xunjun.mo@isl.utoronto.ca

Group Lunch, December 2014

xmas2015lunch

Past Students

Name

Position

Research

More Info

Alireza Sharif-Bakhtiar Ph.D. Low-Power High Speed Optical Links in CMOS
LinkedIn profile
Behzad Dehlaghi Ph.D. Parallel Ultra-Short Reach Die-to-Die Links
LinkedIn profile
Shayan Shahramian Ph.D. Adaptive Decision Feedback Equalization With Continuous-Time Infinite Impulse Response Filters Link to thesis
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Amer Samarah Ph.D. Improved Phase Detection for Digital Phase Locked Loops Link to thesis
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Kevin Banovic Ph.D. Mixed-Signal Architectures for Spectrum Sensing Link to thesis
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Dustin Dunwell Ph.D. Adaptive Receivers for High-Speed Wireline Links Download thesis
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Kentaro Yamamoto Ph.D. A 1-1-1-1 MASH Delta-Sigma ADC using Dynamic Comparator-based OTAs Link to thesis
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Mike Bichan Ph.D. Parallel chip-to-chip I/O Link to thesis
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Shahriar Shahramian Ph.D. Ultra-high-speed A/D conversion Link to thesis
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Masum Hossain Ph.D. Low-power Multi-Gbps Wireline Communication Link to thesis
Faculty page at U. Alberta
Ahmad Darabiha Ph.D. High-throughput low-density parity check decoders LinkedIn profile
Download thesis
Faisal Musa Ph.D. High-speed baud-rate clock recovery LinkedIn profile
Link to thesis
Yue Yin M.A.Sc. The Role of Voltage Regulation in Power Integrity for Multi-Gbps Parallel I/O Interfaces Link to thesis
LinkedIn profile
Nadeesha Amarasinghe M.A.Sc. A Single-ended Simultaneously Bidirectional Transceiver for Ultra-short Reach Die to Die Links Link to thesis
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Masumi Shibata M.A.Sc. CMOS VCSEL Driver Circuit for 25+Gbps/channel Short-reach Parallel Optical Links Link to thesis
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Victor Kozlov M.A.Sc. Capacitively-Coupled CMOS VCSEL Driver Circuits for Optical Communication Link to thesis
LinkedIn profile
Jeffrey Wang M.A.Sc. A 1.25GS/S 8-bit Time-Interleaved C-2C SAR ADC for Wireline Receiver Applications Link to thesis
Web Link
Luke Wang M.A.Sc. Timing Skew Calibration for Time Interleaved Analog to Digital Converters Link to thesis
Web Link
Alain Rousson M.A.Sc. A 2-lane 2Gbps optical receiver with integrated photodiodes in 90nm CMOS Link to thesis
LinkedIn profile
Hemesh Yasotharan M.A.Sc. High-performance CMOS photo-receivers Link to thesis
LinkedIn profile
Tony Kao M.A.Sc. A 5-Gbps Optical Receiver with Monolithically Integrated Photodetector in 0.18-um CMOS Download thesis
LinkedIn profile
Peter Park M.A.Sc. A 4PAM/2PAM coaxial cable receiver analog front-end targeting 40Gb/s in 90-nm CMOS Link to thesis
George Ng M.A.Sc. Distributed Circuit Techniques for Equalization of Short Multimode Fiber Links Link to thesis
Horace Cheng M.A.Sc. A 4PAM/2PAM Coaxial Cable Driver Targeting 40Gb/s in 0.13µm CMOS Download thesis
Jennifer Pham M.A.Sc. Time-interleaved DS-DAC for Broadband Wireless Applications Download thesis
Kentaro Yamamoto M.A.Sc. A programmable delta-sigma ADC Download thesis
Mike Bichan M.A.Sc. Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links Download thesis
Adesh Garg M.A.Sc. A 1-tap 40-Gbps look-ahead decision feedback equalizer in SiGe BiCMOS Download thesis
Jonathan Sewter M.A.Sc. Electronic equalization of polarization-mode dispersion in 40-Gb/s optical systems Download thesis
Sabrina Liao B.A.Sc. Broadband CMOS Digitally-controlled Oscillators LinkedIn profile
Michael Georgas B.A.Sc. A Genetic Algorithm for the Design of Passive Filters and a Distributed Amplifier Download thesis
LinkedIn profile
Denis Daly B.A.Sc. Direct GMSK generation using delta-sigma modulation Download thesis
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Shuai Chen Post-Doctoral Fellow Optical CMOS Receiver for VCSEL-Based PAM Links Institute of Computing Technology, Chinese Academy of Sciences