Check out our article in the IEEE Solid-State Circuits Magazine. We overview die-to-die interconnect technology that has paved the way for chiplets and is revolutionizing high-performance computing and networking systems.

Two ISL alumni presented back-to-back to a packed crowd of over 400 researchers at the ISSCC 2019 session on “Advanced Wireline Techniques” Wednesday afternoon, February 20th in San Francisco: congratulations to Shayan Shahramian and Masum Hossain. In total, six ISL alumni were authors on ISSCC papers this year.

In partnership with CMC Microsystems, a very successful workshop on Advanced CMOS technologies was held here at U of T, December 6 & 7, 2018. The event was sold out, with industry and academic attendees from across the country. Prof. Chan Carusone presented the opening remarks and moderated the closing panel session.

Prof. Chan Carusone delivered seminars in Melbourne and Sydney, Australia on CMOS Optical Transceiver circuits, March 15 and 28th, 2018.

Congratulations to ISL Ph.D. candidate Luke Wang who will be presenting his work on a “A 64Gb/s PAM-4 Transceiver Utilizing an Adaptive Threshold ADC in 16nm FinFET” at the 2018 International Solid-State Circuits Conference in San Franscisco.  The work is part of our collaboration with Huawei Canada, and is the only university-led paper at the conference describing a circuit in 16nm CMOS.  Check out the conference advance program here.

Prof. Chan Carusone delivered a webinar on CMOS Transceiver Circuits for Short-Reach Optical Communication attended live by 100’s of engineers from around the world.  It is now available from the IEEE Solid-State Circuits Society (free for members).

Prof. Chan Carusone is giving a seminar to analog/mixed-signal design researchers at Texas A&M University on “CMOS Transceiver Circuits For Short-Reach Optical Communication” on the afternoon of May 3rd. 

Three papers from ISL have been accepted for presentation at this year’s Custom Integrated Circuits Conference in May in Austin, Texas, including a benchmark low-power LTE receiver, and transceiver circuits for short-reach optical communication up to 40Gbps.

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Prof. Chan Carusone presented a tutorial on Signal Integrity Analysis for Gb/s Links at the International Solid-State Circuits Conference in San Francisco February 5, 2017. Signal integrity analysis permits circuit designers to model and evaluate high-speed I/O with fast simulations, both for quick evaluation of design alternatives and accurate high-level verification. This tutorial covers theoretical underpinnings and practical tools for behavioral modeling and simulation of wireline chip-to-chip links. Attendees learn to accurately model lossy interconnect, packaging parasitics, and transceiver front-ends. Nondeterministic impairments such as noise and jitter, and the modeling of linear and decision-feedback equalization, are also treated. Analysis techniques amenable to both circuit-level (netlist) simulators and high-level modeling (e.g. Matlab) tools are covered.

Prof. Chan Carusone was an invited speaker at the IEEE Second Workshop on Solid State Circuits – Design, Technology and Applications in Bucharest, Romania, and at the Tyndall National Institute, Cork, Ireland in October 2016.